Full pin assignment of the FPGAedu Board v1.
| Phys pin | FPGA signal | Suggested function |
|---|
| 1 | GND | Ground |
| 2 | 3V3 | 3.3 V supply |
| 3 | IO_2 | GPIO / SPI MOSI |
| 4 | IO_3 | GPIO / SPI MISO |
| 5 | IO_4 | GPIO / SPI SCK |
| 6 | IO_5 | GPIO / SPI CS |
| 7 | IO_6 | GPIO / I2C SDA |
| 8 | IO_7 | GPIO / I2C SCL |
| Phys pin | FPGA signal | Suggested function |
|---|
| 1 | GND | Ground |
| 2 | 5V | 5 V supply |
| 3 | IO_10 | GPIO / UART TX |
| 4 | IO_11 | GPIO / UART RX |
| 5 | IO_12 | GPIO / PWM |
| 6 | IO_13 | GPIO / ADC trigger |
| Label | FPGA signal | Type |
|---|
| D1..D8 | LED_1..8 | Output |
| BTN1..4 | BTN_1..4 | Input |
| CLK | clk | 12 MHz |
Remember to use set_io in your .pcf file to map these pins to your Verilog signals.
